1. Field of the Invention
The present invention relates to a device structure of a semiconductor device, particularly, a MOS transistor and a manufacturing method thereof, and more particularly, a high-performance one-transistor floating-body DRAM cell device having a double-gate structure where the one gate is a gate of a general MOS device and the other is a control electrode having a non-volatile memory function, a manufacturing method thereof, and a cell array of the devices.
2. Description of the Related Art
An existing DRAM cell device is constructed with one MOS transistor and one cell capacitor. Recently, as a degree of integration in a DRAM is increasingly required, a size of a cell device needs to be reduced, and a size of a cell capacitor needs to be reduced. Such a miniaturization of the cell device and the cell capacitor in the MOS device requires very difficult manufacturing processes. Recently, MOS devices having a floating body have been as DRAM cell devices. In the devices, DRAM memory operations can be performed by storing or removing charges in the floating body. In this technology, since one MOS cell device is used, the DRAM can be implemented by using simple processes unlike the conventional DRAM. Such a DRAM cell device is referred to as a one-transistor floating-body DRAM cell device (hereinafter, simply referred to as a one-transistor DRAM cell device or a 1T-DRAM cell device). The one-transistor DRAM cell device can be adapted to an existing DRAM. In addition, the one-transistor DRAM cell device can be embedded in an existing logic circuit (for example, a micro-processor or a network-processor). In this case, the one-transistor DRAM cell device is called as an eDRAM cell device. The one-transistor DRAM cell device used in the eDRAM has a high memory capacity or a high operating speed, so that its applications are increased. The one-transistor DRAM cell device has a floating body. The adjacent floating bodies are electrically isolated from each other so as to be floated. Information is stored in the floating body. Therefore, unlike a conventional DRAM cell device, in the one-transistor DRAM cell device, no cell capacitor is required. As a result, a cell area can be reduced, and a degree of integration of the DRAM cell devices can be improved.
FIG. 1 shows a conventional one-transistor DRAM cell device which is implemented on an SOI (Silicon On Insulator) substrate. The SOI substrate is a single-crystalline silicon film where a substrate 1, a buried insulating layer 2, a source 8, a drain 9, and a floating body 3 are formed. The source 8 and the drain 9 are disposed at both sides of the floating body 3. A gate insulating layer 10 is formed on the silicon film, and a gate electrode 11 is disposed on the gate insulating layer.
Now, operations of the conventional one-transistor DRAM cell device shown in FIG. 1 will be described in brief. The description is made under the assumption that the DRAM cell device is an NMOS device. However, the same description can be adapted to a PMOS device. Firstly, a write-1 operation is described. A source 8 is grounded, a drain 9 that is a bit line and a gate electrode 11 that is a word line are applied with voltages so that impact ionization can be easily formed. As a result, holes are generated in the floating body in the vicinity of the drain region 9. Some of the holes are accumulated in the floating body 3, and others are flown to the source region 8 over an potential barrier. A threshold voltage of the device is changed according to a concentration of the holes accumulated in the floating body 3. As a result, a drain current in a given read operation is changed. According to the write-1 operation, excessive holes exist in the floating body 3, so that the threshold voltage of the device is lowered. As a result, the drain current is increased. Now, the read operation is described. A voltage equal to or higher than the threshold voltage is applied to the gate electrode 11, and a bit-line read voltage lower than that of the write-1 operation is applied to the drain. According to whether the holes in the floating body 3 are excessive or depleted by the erase operation, the drain current is varied. The information in the cell is identified according to the difference in the drain current.
Next, a write-0 operation is described. If the gate electrode 11 is applied with a suitable voltage and if the drain 9 is applied with a negative voltage, the holes in the floating body are flown into the drain 9. Therefore, the floating body 3 is in the hole-deficient state, so that the threshold voltage of the device is increased. The one-transistor DRAM cell device is disclosed in U.S. Pat. No. 7,239,549.
A method using GIDL (Gate Induced Drain Leakage) as another example of the write-1 operation is described. A voltage of 0V or a negative voltage is applied to the gate of the device, and a positive voltage is applied to the drain 9 connected to the bit line. Therefore, electron-hole pairs are generated due to band-to-band tunneling in a region where the drain and the gate are overlapped with each other. The electrons are flown into the drain 9, and the holes are stored in the floating body 3.
FIG. 1 shows a miniaturization of a gate length from a left structure to a right structure. Since the miniaturization of device leads to an increase in capacity of DRAM, it is very important. However, due to the miniaturization of channel length, a short channel effect occurs. In addition, a size of a floating body which stores information is reduced, so that a difference in drain current between the write-1 state and the write-0 state is decreased. Accordingly, it is difficult to sense and to store information for a long time.
In order to solve the problem, one-transistor DRAM cell devices having a double-gate structure that is effective in the miniaturization of device have been proposed. Now, three representative structures among the proposed double-gate structures are described. FIGS. 2(a) to (c) show the proposed double-gate structures. An upper gate electrode 11 and a substrate are used, or an additional electrode is inserted as a lower electrode. FIGS. 1(a) and (b) show the proposed one-transistor DRAM cell device. In FIG. 1(a), a lower electrode (not shown) is provided to be independent of the substrate 1. In FIG. 1(b), the substrate 1 has a function as a lower electrode. In the cell devices, by using a bias of the lower electrode, holes can be held in the floating body 3 for a long time, and a sensing margin can be improved. Hereinafter, the structures will be described in detail.
FIG. 2(a) shows an example of a conventional one-transistor DRAM cell device published in UC Berkeley (Charles Kuo et al, “A Capacitor-less Double Gate DRAM Technology for Sub-100-nm Embedded and Stand-Alone Memory Applications,” IEEE Trans. on Electron Devices, vol. 50, no. 12, pp. 2408-2416, 2003). In the example, an upper gate 11 and a lower gate 25 are disposed on and under a floating body 3, respectively, so that the upper gate 11 and the lower gate 25 are electrically independent of each other. In the one-transistor DRAM cell device, due to the characteristics of the double-gate structure, it is possible to suppress the short channel effect and to improve the sensing margin. In the cell device, a negative voltage (for example, −1V) is applied to the lower gate 25, so that the holes can be held in the floating body 3 in the write-1 operation for a long time. In addition, during an erase operation, a voltage of 0V is applied to the lower gate 25, so that the holes in the floating body 3 can be effectively flown into a drain region. Accordingly, it is possible to improve the sensing margin. However, the one-transistor DRAM cell device has the problems as follows. Generally, in a case where the floating body 3 in the double-gate structure has a small thickness and is completed depleted, a width of the body needs to be small so as to suppress the short channel effect. A threshold voltage of the double-gate device having a completely-depleted body depends on the thickness of the body and a doping concentration of the body. Although a completely-depleted device is actually manufactured, a dispersion of the threshold voltages among the cell devices is too large, so that it is difficult to implement a practical device. In addition, the lower gate electrode 25 needs to be independently provided to each cell device, there is a problem in that a degree of integration of cell devices is greatly decreased in a layout of a cell array of the cell devices.
FIG. 2(b) shows another example of a conventional one-transistor DRAM cell device having a double-gate structure published by Samsung electronics (Chang Woo Oh et al, “Floating Body DRAM Characteristics of Silicon-On-ONO (SOONO) Devices for System-on-Chip (SoC) Applications” in VLSI Tech., Dig., 2007, pp. 168-169.). In the cell device, an existing bulk silicon substrate is used as a substitute for an SOI substrate, and an SiGe film is used as a sacrificial layer so as to implement a floating body 3. In FIG. 2(b), spaces filled with a fourth insulating layer 21 and a first nitride layer 22 are the regions where the SiGe film initially exists. A thickness of the insulating layers is about 50 nm. In the cell device, in order to obtain the double-gate effect, the substrate 1 is used like a lower electrode. Although the sensing margin can be improved due to the double-gate effect, the one-transistor DRAM cell device has the problems as follows. Firstly, since a thickness (about 50 nm in the example) of the insulating layer formed between the lower gate electrode 7 and the floating body 3 is too large, a high voltage of about −5V needs to be always applied so as to store holes in the body. The thickness of the insulating layer may be reduced by reducing a thickness of the sacrificial layer of the SiGe layer in the cell device manufacturing processes. However, if the thickness is reduced, much difficulty is involved with the processes. Secondly, since the substrate 1 is used as the lower gate electrode, the substrate is common to the all cell devices, so that it is impossible to apply a bias to a specific cell device or to cell device in a specific region. In addition, in order to independently provide the lower gate electrodes 7 to the cell devices, that is, in order to independently form the lower gate electrodes, wells may be formed in the substrate 1. However, in this case, since an interval between the wells needs to be enlarged, a degree of integration is greatly decreased. Thirdly, as described in FIG. 2(a), since a completely-depleted floating body needs to be used, there is an elementary problem in that a dispersion of read currents among the cell devices is increased.
FIG. 2(c) shows still another example a double-gate structure published in Cornell University (Arvind Kumar et al, “Scaling of Flash NVRAM to 10's of nm by Decoupling of Storage from Read/Sense Using Back-Floating Gates,” IEEE Trans. on Nanotechnology, vol. 1, no. 4, pp. 247-254, December 2002). The double-gate structure is contrived for an exiting flash memory but a one-transistor DRAM cell device. According to the published document, write/erase operations are performed by storing or removing charges in a floating storage node through a bottom electrode 23, and a memory storage state is read by using an upper gate electrode 11. However, according to the published result, a change in threshold voltage in the write/erase operations in the device is not good. Although the structure is contrived for a flash device, the structure may be adapted to a one-transistor DRAM cell device. However, there is no published one-transistor DRAM cell device using the structure. If the structure is directly adapted to the one-transistor DRAM cell device, there are problems as follows. Firstly, since a thickness of an insulating layer interposed between a floating body 3 and a bottom electrode 23 having an effect of a lower electrode is too large, a very high voltage needs to be applied to the bottom electrode 23 so as to obtain the double-gate effect. If a thickness of insulating layers on and under a floating storage node 4 is reduced so as to reduce the voltage, the device cannot be operated as a suitable flash memory. In particular, since the floating storage node 24 in the published structure is a conductive layer, a thickens of a tunneling insulating layer disposed thereon needs to be at least about 7 nm so as not to lose information. Secondly, since the bottom electrodes 23 formed in the substrate 1 are not electrically isolated between the cell devices, a lower electrode effect for a specific cell device or for a plurality of cell devices in a specific region cannot be reduced. In the published document, in order to form the bottom electrode, a highly-doped substrate or a substrate of which upper portion is highly doped is used. That is, the bottom substrate 23 is formed by doping the substrate with impurities. In this case, since an interval between the bottom electrodes 23 of the cell devices needs to be enlarged so as to electrically independently provide the bottom electrodes 23 to the cell devices, there is a problem in that a degree of integration in a cell array of the cell device is greatly decreased. Thirdly, as described above with reference to FIGS. 2(a) and (b), since the dispersion of the threshold voltages among the cell devices having completely-depleted floating body 3 is too large, it is difficult to practically implement the one-transistor DRAM cell device without a special method.